View 3724MPFE_7489003.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lt3724 1 3724fc typical application features applications description high voltage, current mode switching regulator controller the lt ? 3724 is a dc/dc controller used for medium power, low part count, low cost, high ef? ciency supplies. it of- fers a wide 4v-60v input range (7.5v minimum startup voltage) and can implement step-down, step-up, inverting and sepic topologies. the lt3724 includes burst mode operation, which re- duces quiescent current below 100a and maintains high ef? ciency at light loads. an internal high voltage bias regulator allows for simple biasing and can be back driven to increase ef? ciency. additional features include ? xed frequency current mode control for fast line and load transient response; a gate driver capable of driving large n-channel mosfets; a precision undervoltage lockout function; 10a shutdown current; short-circuit protection; and a programmable soft-start function that directly controls output voltage slew rates at startup which limits inrush current, minimizes overshoot and facilitates supply sequencing. the lt3724 is available in a 16-lead thermally enhanced tssop package. l , lt, ltc and ltm are registered trademarks of linear technology corporation. burst mode is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5731694, 6498466, 6611131. high voltage step-down regulator n wide input range: 4v to 60v n output voltages up to 36v (step-down) n burst mode ? operation: <100a supply current n 10a shutdown supply current n 1.3% reference accuracy n 200khz fixed frequency n drives n-channel mosfet n programmable soft-start n programmable undervoltage lockout n internal high voltage regulator for gate drive n thermal shutdown n current limit unaffected by duty cycle n 16-pin thermally enhanced tssop package n industrial power distribution n 12v and 42v automotive and heavy equipment n high voltage single board systems n distributed power systems n avionics n telecom power ef? ciency and power loss vs load current v in shdn c ss burst_en v fb v c sgnd boost tg sw v cc pgnd sense + sense C v in 30v to 60v v out 24v 75w 3724 ta01a lt3724 1m 68.1k 1000pf 4.99k 93.1k 10 200k 0.22 f c out 330 f c in 68 f 1 f 47 h 0.025 si7852 ss3h9 120pf 680pf 40.2k + load current (a) 0.1 efficiency (%) power loss (w) 95 90 85 80 75 70 65 12 10 8 6 4 2 0 110 3724 ta01b v in = 48v loss efficiency
lt3724 2 3724fc pin configuration absolute maximum ratings input supply voltage (v in ) ......................... 65v to C0.3v boosted supply voltage (boost) .............. 80v to C0.3v switch voltage (sw)(note 8) ........................ 65v to C1v differential boost voltage (boost to sw) ...................................... 24v to C0.3v bias supply voltage (v cc ) .......................... 24v to C0.3v sense + and sense C voltages ................... 40v to C0.3v (sense + to sense C ) ................................... 1v to C1v burst_en voltage .................................... 24v to C0.3v v c , v fb , c ss , and shdn voltages................. 5v to C0.3v c ss and shdn pin currents .....................................1ma operating junction temperature range (notes 2, 3) lt3724e ............................................. C40c to 125c lt3724i .............................................. C40c to 125c lt3724mp.......................................... C55c to 125c storage temperature .............................. C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 v in nc shdn c ss burst_en v fb v c sgnd boost tg sw nc v cc pgnd sense + sense C 17 t jmax = 125c, ja = 40c/w, jc = 10c/w exposed pad is sgnd (pin 17), must be soldered to pcb electrical characteristics order information lead free finish tape and reel part marking package description temperature range lt3724efe#pbf lt3724efe#trpbf 3724efe 16-lead plastic tssop C40c to 125c lt3724ife#pbf lt3724ife#trpbf 3724ife 16-lead plastic tssop C40c to 125c lead based finish tape and reel part marking* package description temperature range lt3724MPFE lt3724MPFE#tr 3724MPFE 16-lead plastic tssop C55c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 20v, v cc = boost = burst_en = 10v, shdn = 2v, sense C = sense + = 10v, sgnd = pgnd = sw = 0v, unless otherwise noted. symbol parameter conditions min typ max units v in operating voltage range (note 4) minimum start voltage uvlo threshold (falling) uvlo threshold hysteresis 4 7.5 3.65 3.8 670 60 3.95 v v v mv i vin v in supply current v in burst mode current v in shutdown current v cc > 9v v burst_en = 0v, v fb = 1.35v v shdn = 0v 20 20 10 15 a a a
lt3724 3 3724fc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 20v, v cc = boost = burst_en = 10v, shdn = 2v, sense C = sense + = 10v, sgnd = pgnd = sw = 0v, unless otherwise noted. symbol parameter conditions min typ max units v boost operating voltage range operating voltage range (note 5) uvlo threshold (rising) uvlo threshold hysteresis v boost - v sw v boost - v sw v boost - v sw 5 400 75 20 v v v mv i boost boost supply current (note 6) boost burst mode current boost shutdown current v burst_en = 0v v shdn = 0v 1.4 0.1 0.1 ma a a v cc operating voltage range (note 5) output voltage uvlo threshold (rising) uvlo threshold hysteresis over full line and load range 8 6.25 500 20 8.3 v v v mv i vcc v cc supply current (note 6) v cc burst mode current v cc shutdown current short-circuit current v burst_en = 0v v shdn = 0v C30 1.7 80 20 C55 2.1 ma a a ma v fb error amp reference voltage measured at v fb pin 1.224 1.215 1.231 1.238 1.245 v v i fb feedback input current 25 na v shdn enable threshold (rising) threshold hysteresis 1.3 1.35 120 1.4 v mv v sense common mode range current limit sense voltage v sense + C v sense C 0 140 150 36 175 v mv i sense input current (i sense + + i sense C ) v sense(cm) = 0v v sense(cm) = 2.5v v sense(cm) > 4v 400 2 C150 a a a f sw operating frequency mp grade 190 175 165 200 200 210 220 225 khz khz khz v fb(ss) soft-start disable voltage soft-start disable hysteresis v fb rising 1.185 300 v mv i ss soft-start capacitor control current 2 a g m error amp transconductance 275 340 400 mhos a v error amp dc voltage gain 62 db v c error amp output range zero current to current limit 1.2 v i vc error amp sink/source current 30 a v tg gate drive output on voltage (note 7) gate drive output off voltage c load = 3300pf c load = 3300pf 9.8 0.1 v v t tg gate drive rise/fall time 10% to 90% or 90% to 10%, c load = 3300pf 60 ns t tg(off) minimum switch off time 350 ns t tg(on) minimum switch on time 300 500 ns i sw sw pin sink current v sw = 2v 300 ma
lt3724 4 3724fc typical performance characteristics shutdown threshold (rising) vs temperature shutdown threshold (falling) vs temperature v cc vs temperature v cc vs i cc(load) v cc vs v in i cc current limit vs temperature 3724 g01 shutdown threshold, rising (v) 1.38 1.37 1.36 1.35 1.34 1.33 1.32 temperature ( c) C50 25 75 C25 0 50 100 125 3724 g02 temperature ( c) C50 shutdown threshold, falling (v) 1.26 1.25 1.24 1.23 1.22 1.21 1.20 25 75 C25 0 50 100 125 temperature ( c) C50 25 75 C25 0 50 100 125 3724 g03 8.2 8.1 8.0 7.9 7.8 7.7 7.6 7.5 v cc (v) i cc = 20ma 3724 g04 i cc (load) (ma) 0 8.2 8.1 8.0 7.9 7.8 7.7 7.6 7.5 15 25 510 20 30 35 v cc (v) t a = 25 c 3724 g05 v in (v) v cc (v) 9 8 7 6 5 4 3 4 6 8 9 57 10 11 12 i cc = 20ma t a = 25 c temperature ( c) C50 25 75 C25 0 50 100 125 3724 g06 i cc current limit (ma) 70 60 50 40 30 20 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3724 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 3: the lt3724e is guaranteed to meet performance speci? cations from 0c to 125c junction temperature. speci? cations over the C 40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3724i is guaranteed over the full C40c to 125c operating junction temperature range. the lt3724mp is 100% tested and guaranteed over the C55c to 125c operating junction temperature range. note 4: v in voltages below the start-up threshold (7.5v) are only supported when the v cc is externally driven above 6.5v. note 5: operating range is dictated by mosfet absolute maximum v gs . note 6: supply current speci? cation does not include switch drive currents. actual supply currents will be higher. note 7: dc measurement of gate drive output on voltage is typically 8.6v. internal dynamic bootstrap operation yields typical gate on voltages of 9.8v during standard switching operation. standard operation gate on voltage is not tested but guaranteed by design. note 8: the C1v absolute maximum on the sw pin is a transient condition. it is guaranteed by design and not subject to test. electrical characteristics
lt3724 5 3724fc v cc uvlo threshold (rising) vs temperature i cc vs v cc ( shdn = 0v) error amp transconductance vs temperature typical performance characteristics i (sense + + sense C ) vs v sense (cm) operating frequency vs temperature error amp reference vs temperature maximum current sense threshold vs temperature v in uvlo threshold (rising) vs temperature v in uvlo threshold (falling) vs temperature 3724 g07 temperature ( c) C50 25 75 C25 0 50 100 125 v cc uvlo threshold, rising (v) 6.5 6.4 6.3 6.2 6.1 6.0 3724 g08 v cc (v) 0 i cc ( a) 15 20 25 16 10 5 0 246 810 12 14 18 20 t a = 25 c temperature ( c) C50 error amp transconductance ( mhos) 350 345 340 335 330 325 320 25 75 3724 g09 C25 0 50 100 125 v sense (cm) (v) 0 i (sense + + sense C ) ( a) 400 300 200 100 0 C100 C200 0.5 1.0 1.5 2.0 3724 g10 2.5 4.5 3.5 5.0 4.0 3.0 t a = 25 c temperature ( c) C50 operating frequency (khz) 230 220 210 200 190 180 170 25 75 3724 g11 C25 0 50 100 125 temperature ( c) C50 25 75 3724 g12 C25 0 50 100 125 1.234 1.233 1.232 1.231 1.230 1.229 1.228 1.227 error amp reference (v) temperature ( c) C50 25 75 C25 0 50 100 125 current sense threshold (mv) 160 158 156 154 152 150 148 146 144 142 140 3724 g13 temperature ( c) C50 25 75 C25 0 50 100 125 3724 g14 4.54 4.52 4.50 4.48 4.46 4.44 4.42 4.40 v in uvlo threshold, rising (v) temperature ( c) C50 25 75 C25 0 50 100 125 3724 g15 v in uvlo threshold, falling (v) 3.86 3.84 3.82 3.80 3.78 3.76
lt3724 6 3724fc pin functions v in (pin 1): the v in pin is the main supply pin and should be decoupled to sgnd with a low esr capacitor located close to the pin. nc (pin 2): no connection. shdn (pin 3): the shdn pin has a precision ic enable threshold of 1.35v (rising) with 120mv of hysteresis. it is used to implement an undervoltage lockout (uvlo) circuit. see application information section for implementing a uvlo function. when the shdn pin is pulled below a transistor v be (0.7v), a low current shutdown mode is entered, all internal circuitry is disabled and the v in sup- ply current is reduced to approximately 10a. typical pin input bias current is <10a and the pin is internally clamped to 6v. c ss (pin 4): the soft-start pin is used to program the sup- ply soft-start function. the pin is connected to v out via a ceramic capacitor (c ss ) and 200k series resistor. during start-up, the supply output voltage slew rate is controlled to produce a 2a average current through the soft-start coupling capacitor. use the following formula to calculate c ss for a given output voltage slew rate: c ss = 2a(t ss /v out ) see the application section for more information on setting the rise time of the output voltage during start-up. shorting this pin to sgnd disables the soft-start function. burst_en (pin 5): the burst_en pin is used to enable or disable burst mode operation. connect the burst_en pin to ground to enable the burst mode function. connect the pin to v cc to disable the burst mode function. v fb (pin 6): the output voltage feedback pin, v fb , is externally connected to the supply output voltage via a resistive divider. the v fb pin is internally connected to the inverting input of the error ampli? er. in regulation, v fb is 1.231v. v c (pin 7): the v c pin is the output of the error ampli? er whose voltage corresponds to the maximum (peak) switch current per oscillator cycle. the error ampli? er is typically con? gured as an integrator circuit by connecting an rc network from the v c pin to sgnd. this circuit creates the dominant pole for the converter regulation control loop. speci? c integrator characteristics can be con? gured to optimize transient response. connecting a 100pf or greater high frequency bypass capacitor from this pin to ground is recommended. when burst mode operation is enabled (see pin 5 description), an internal low impedance clamp on the v c pin is set at 100mv below the burst threshold, which limits the negative excursion of the pin voltage. therefore, this pin cannot be pulled low with a low imped- ance source. if the v c pin must be externally manipulated, do so through a 1k series resistance. sgnd (pin 8, 17): the sgnd pin is the low noise ground reference. it should be connected to the Cv out side of the output capacitors. careful layout of the pcb is necessary to keep high currents away from this sgnd connection. see the application information section for helpful hints on pcb layout of grounds. sense C (pin 9): the sense C pin is the negative input for the current sense ampli? er and is connected to the v out side of the sense resistor for step-down applications. the sensed inductor current limit is set to 150mv across the sense inputs. sense + (pin 10): the sense + pin is the positive input for the current sense ampli? er and is connected to the induc- tor side of the sense resistor for step-down applications. the sensed inductor current limit is set to 150mv across the sense inputs. pgnd (pin 11): the pgnd pin is the high-current ground reference for internal low side switch and the v cc regulator circuit. connect the pin directly to the negative terminal of the v cc decoupling capacitor. see the application informa- tion section for helpful hints on pcb layout of grounds.
lt3724 7 3724fc pin functions v cc (pin 12): the v cc pin is the internal bias supply decou- pling node. use low esr 1f ceramic capacitor to decouple this node to pgnd. most internal ic functions are powered from this bias supply. an external diode connected from v cc to the boost pin charges the bootstrapped capacitor during the off-time of the main power switch. back driving the v cc pin from an external dc voltage source, such as the v out output of the buck regulator supply, increases overall ef? ciency and reduces power dissipation in the ic. in shutdown mode this pin sinks 20a until the pin voltage is discharged to 0v. nc (pin 13): no connection. sw (pin 14): in step-down applications the sw pin is connected to the cathode of an external clamping schottky diode, the drain of the power mosfet and the inductor. the sw node voltage swing is from v in during the on- time of the power mosfet, to a schottky voltage drop below ground during the off-time of the power mosfet. in start-up and in operating modes where there is insuf- ? cient inductor current to freewheel the schottky diode, an internal switch is turned on to pull the sw pin to ground so that the boost pin capacitor can be charged. give careful consideration in choosing the schottky diode to limit the negative voltage swing on the sw pin. tg (pin 15): the tg pin is the bootstrapped gate drive for the top n-channel mosfet. since very fast high cur- rents are driven from this pin, connect it to the gate of the power mosfet with a short and wide, typically 0.02 width, pcb trace to minimize inductance. boost (pin 16): the boost pin is the supply for the bootstrapped gate drive and is externally connected to a low esr ceramic boost capacitor referenced to sw pin. the recommended value of the boost capacitor,c boost , is 50 times greater that the total input capacitance of the topside mosfet. in most applications 0.1f is adequate. the maximum voltage that this pin sees is v in + v cc , ground referred. exposed pad (sgnd) (pin 17): the exposed leadframe is internally connected to the sgnd pin. solder the exposed pad to the pcb ground for electrical contact and optimal thermal performance.
lt3724 8 3724fc functional diagram C + C + C + C + C + v in uvlo (<4v) bst uvlo 8v v cc regulator feedback reference C + 1.231v 3.8v regulator internal supply rail 1 8 7 v in v cc uvlo (<6v) shdn drive control nol switch logic drive control burst_en v c c ss sense C v fb C + 1.185v ~1v 0.5v 2 a burst mode operation soft-start disable/burst enable r s q oscillator slope comp generator boost tg m1 d2 d3 d1 l1 (optional) r sense sw v cc pgnd sense + sgnd 3724 fd boosted switch driver current sense comparator g m error amp 11 12 14 9 10 6 4 c c2 c c1 r1 ra rb v in c in r2 c ss 5 3 16 15 c boost v out c out c vcc C + r c
lt3724 9 3724fc operation the lt3724 is a pwm controller with a constant frequency, current mode control architecture. it is designed for low to medium power, switching regulator applications. its high operating voltage capability allows it to step-up or down input voltages up to 60v without the need for a transformer. the lt3724 is used in nonsynchronous applications, meaning that a freewheeling recti? er diode (d1 of function diagram) is used instead of a bottom side mosfet. for circuit operation, please refer to the functional diagram of the ic and typical application on the front page of the data sheet. the lt3800 is a similar part that uses synchronous recti? cation, replacing the diode with a mosfet in a step-down application. main control loop during normal operation, the external n-channel mosfet switch is turned on at the beginning of each cycle. the switch stays on until the current in the inductor exceeds a current threshold set by the dc control voltage, v c , which is the output of the voltage control loop. the voltage control loop monitors the output voltage, via the v fb pin voltage, and compares it to an internal 1.231v reference. it increases the current threshold when the v fb voltage is below the reference voltage and decreases the current threshold when the v fb voltage is above the reference voltage. for instance, when an increase in the load current occurs, the output voltage drops causing the v fb voltage to drop relative to the 1.231v reference. the voltage control loop senses the drop and increases the current threshold. the peak inductor current is increased until the average inductor current equals the new load current and the output voltage returns to regulation. current limit/short-circuit the inductor current is measured with a series sense resistor (see the typical application on the front page). when the voltage across the sense resistor reaches the maximum current sense threshold, typically 150mv, the tg mosfet driver is disabled for the remainder of that cycle. if the maximum current sense threshold is still ex- ceeded at the beginning of the next cycle, the entire cycle is skipped. cycle skipping keeps the inductor currents to a reasonable value during a short-circuit, particularly when v in is high. setting the sense resistor value is discussed in the application information section. v cc /boosted supply an internal v cc regulator provides v in derived gate-drive power for start-up under all operating conditions with mosfet gate charge loads up to 90nc. the regulator can operate continuously in applications with v in voltages up to 60v, provided the v in voltage and/or mosfet gate charge currents do not create excessive power dissipa- tion in the ic. safe operating conditions for continuous regulator use are shown in figure 1. in applications where these conditions are exceeded, v cc must be derived from an external source after start-up. the lt3724 regulator can, however, be used for full time use in applications where short-duration v in transients exceed allowable continuous voltages. for higher converter ef? ciency and less power dissipa- tion in the ic, v cc can also be supplied from an external supply such as the converter output. when an external supply back drives the internal v cc regulator through an external diode and the v cc voltage is pulled to a diode above its regulation voltage, the internal regulator is dis- abled and goes into a low current mode. v cc is the bias supply for most of the internal ic functions and is also used to charge the bootstrapped capacitor (c boost ) via an external diode. the external mosfet switch is biased from the bootstrapped capacitor. while the external mosfet switch is off, an internal bjt switch, whose collector is connected to the sw pin and emitter is connected to the pgnd pin, is turned on to pull the sw node to pgnd and recharge the bootstrap capacitor. the switch stays on until figure 1. v cc regulator continuous operating conditions mosfet total gate charge (nc) 0 v in (v) 70 60 50 40 30 20 10 20 40 60 80 3724 f01 100 safe operating area (refer to functional diagram)
lt3724 10 3724fc operation either the start of the next cycle or until the bootstrapped capacitor is fully charged. mosfet driver the lt3724 contains a high speed boosted driver to turn on and off an external n-channel mosfet switch. the mosfet driver derives its power from the boost capaci- tor which is referenced to the sw pin and the source of the mosfet. the driver provides a large pulse of current to turn on the mosfet fast to minimize transition times. multiple mosfets can be paralleled for higher current operation. to eliminate the possibility of shoot through between the mosfet and the internal sw pull-down switch, an adap- tive nonoverlap circuit ensures that the internal pull-down switch does not turn on until the gate of the mosfet is below its turn on threshold. low current operation (burst mode operation) to increase low current load ef? ciency, the lt3724 is capable of operating in linear technologys proprietary burst mode operation where the external mosfet operates intermittently based on load current demand. the burst mode function is disabled by connecting the burst_en pin to v cc and enabled by connecting the pin to sgnd. when the required switch current, sensed via the v c pin voltage, is below 15% of maximum, burst mode operation is employed and that level of sense current is latched onto the ic control path. if the output load requires less than this latched current level, the converter will overdrive the output slightly during each switch cycle. this overdrive condition is sensed internally and forces the voltage on the v c pin to continue to drop. when the voltage on v c drops 150mv below the 15% load level, switching is disabled, and the lt3724 shuts down most of its internal circuitry, reducing total quiescent current to 100a. when the converter output begins to fall, the v c pin voltage begins to climb. when the voltage on the v c pin climbs back to the 15% load level, the ic returns to normal operation and switching resumes. an internal clamp on the v c pin is set at 100mv below the output disable threshold, which limits the negative excursion of the pin voltage, minimizing the converter output ripple during burst mode operation. during burst mode operation, the v in pin current is 20a and the v cc current is reduced to 80a. if no external drive is provided for v cc , all v cc bias currents originate from the v in pin, giving a total v in current of 100a. burst current can be reduced further when v cc is driven using an output derived source, as the v cc component of v in current is then reduced by the converter duty cycle ratio. start-up the following section describes the start-up of the supply and operation down to 4v once the step-down supply is up and running. for the protection of the lt3724 and the switching supply, there are internal undervoltage lockout (uvlo) circuits with hysteresis on v in , v cc and v boost , as shown in the electrical characteristics table. start-up and continuous operation require that all three of these undervoltage lockout conditions be satis? ed because the tg mosfet driver is disabled during any uvlo fault condition. in startup, for most applications, v cc is powered from v in through the high voltage linear regulator of the lt3724. this requires v in to be high enough to drive the v cc voltage above its undervoltage lockout threshold. v cc , in turn, has to be high enough to charge the boost capacitor through an external diode so that the boost voltage is above its undervoltage lockout threshold. there is an npn switch that pulls the sw node to ground each cycle during the tg power mosfet off-time, ensuring the boost capacitor is kept fully charged. once the supply is up and running, the output voltage of the supply can backdrive v cc through an external diode. internal circuitry disables the high voltage regulator to conserve v in supply current. output voltages that are too low or too high to backdrive v cc require additional circuitry such as a voltage doubler or linear regulator. once v cc is backdriven from a supply other than v in , v in can be reduced to 4v with normal operation maintained. (refer to functional diagram)
lt3724 11 3724fc operation soft-start the soft-start function controls the slew rate of the power supply output voltage during start-up. a controlled output voltage ramp minimizes output voltage overshoot, reduces inrush current from the v in supply, and facilitates supply sequencing. a capacitor, c ss , connected between v out of the supply and the c ss pin of the ic, programs the slew rate. the capacitor provides a current to the c ss pin which is proportional to the dv/dt of the output voltage. the soft-start circuit overrides the control loop and adjusts the inductor current until the output voltage slew rate yields a 2a current through the soft-start capacitor. if the current is greater than 2a, then the current threshold set by the dc control voltage, v c , is decreased and the inductor current is lowered. this in turn lowers the output current and the output voltage slew rate is decreased. if the current is less than 2a, then the current threshold set by the dc control voltage, v c , is increased and the inductor current is raised. this in turn increases the output current and the output voltage slew rate is increased. once the output voltage is within 5% of its regulation voltage, the soft-start circuit is disabled and the main control regulates the output. the soft-start circuit is reactivated when the output voltage drops below 70% of its regulation voltage. slope/antislope compensation the ic incorporates slope compensation to eliminate potential subharmonic oscillations in the current control loop. the ics slope compensation circuit imposes an arti? cial ramp on the sensed current to increase the rising slope as duty cycle increases. unfortunately, this additional ramp typically affects the sensed current value, thereby reducing the achievable current limit value by the same amount as the added ramp represents. as such, the current limit is typically reduced as the duty cycle increases. the lt3724, however, contains antislope compensation circuitry to eliminate the current limit reduction associated with slope compensation. as the slope compensation ramp is added to the sensed current, a similar ramp is added to the current limit threshold. the end result is that the current limit is not compromised so the lt3724 can provide full power regardless of required duty cycle. shutdown the lt3724 includes a shutdown mode where all the internal ic functions are disabled and the v in current is reduced to less than 10a. the shutdown pin can be used for undervoltage lockout with hysteresis, micropower shut- down or as a general purpose on/off control of the converter output. the shutdown function has two thresholds. the ? rst threshold, a precision 1.23v threshold with 120mv of hysteresis, disables the converter from switching. the second threshold, approximately a 0.7v referenced to sgnd, completely disables all internal circuitry and reduces the v in current to less than 10a. see the application information section for more information. (refer to functional diagram)
lt3724 12 3724fc the basic lt3724 step-down (buck) application, shown in the typical application on the front page, converts a larger positive input voltage to a lower positive or negative output voltage. this application information section assists selection of external components for the requirements of the power supply. r sense selection the current sense resistor, r sense , monitors the inductor current of the supply (see typical application on front page). its value is chosen based on the maximum required output load current. the lt3724 current sense ampli? er has a maximum voltage threshold of, typically, 150mv. therefore, the peak inductor current is 150mv/r sense . the maximum output load current, i out(max) , is the peak inductor current minus half the peak-to-peak ripple cur- rent, i l . allowing adequate margin for ripple current and external component tolerances, r sense can be calculated as fol- lows: r sense = 100mv i out(max ) typical values for r sense are in the range of 0.005 to 0.05. inductor selection the critical parameters for selection of an inductor are minimum inductance value, volt-second product, satura- tion current and/or rms current. the minimum inductance value is calculated as follows: l v out ? v in(max) ?v out f sw ?v in(max) ? i l f sw is the switch frequency (200khz). the typical range of values for i l is (0.2 ? i out(max) ) to (0.5 ? i out(max) ), where i out(max) is the maximum load current of the supply. using i l = 0.3 ? i out(max) yields a good design compromise between inductor performance versus inductor size and cost. higher values of i l will increase the peak currents, requiring more ? ltering on the input and output of the supply. if i l is too high, the slope compensation circuit is ineffective and current mode instability may occur at duty cycles greater than 50%. lower values of i l require larger and more costly magnetics. a value of i l = 0.3 ? i out(max) produces a 15% of i out(max) ripple current around the dc output current of the supply. some magnetics vendors specify a volt-second product in their datasheet. if they do not, consult the magnetics vendor to make sure the speci? cation is not being exceeded by your design. the volt-second product is calculated as follows: volt-second ( sec) = (v in(max) ?v out )?v out v in(max) ?f s w the magnetics vendors specify either the saturation cur- rent, the rms current or both. when selecting an inductor based on inductor saturation current, use the peak cur- rent through the inductor, i out(max) + i l /2. the inductor saturation current speci? cation is the current at which the inductance, measured at zero current, decreases by a speci? ed amount, typically 30%. when selecting an inductor based on rms current rating, use the average current through the inductor, i out(max) . the rms current speci? cation is the rms current at which the part has a speci? c temperature rise, typically 40c, above 25c ambient. after calculating the minimum inductance value, the volt- second product, the saturation current and the rms current for your design, select an off-the-shelf inductor. a list of magnetics vendors can be found at www.linear.com, or contact the linear technology application department. for more detailed information on selecting an inductor, please see the inductor selection section of linear technology application note 44. step-down converter: mosfet selection the selection criteria of the external n-channel standard level power mosfet include on resistance(r ds(on) ), re- verse transfer capacitance (c rss ), maximum drain source voltage (v dss ), total gate charge (q g ), and maximum continuous drain current. applications information
lt3724 13 3724fc applications information for maximum ef? ciency, minimize r ds(on) and c rss . low r ds(on) minimizes conduction losses while low c rss minimizes transition losses. the problem is that r ds(on) is inversely related to c rss . balancing the transition losses with the conduction losses is a good idea in sizing the mosfet. select the mosfet to balance the two losses. calculate the maximum conduction losses of the mosfet: p cond = (i out(max) ) 2 v out v i n (r ds(on) ) note that r ds(on) has a large positive temperature depen- dence. the mosfet manufacturer?s data sheet contains a curve, r ds(on) vs temperature. calculate the maximum transition losses: p tran = (k)(v in ) 2 (i out(max) )(c rss )(f sw ) where k is a constant inversely related to the gate driver current, approximated by k = 2 for lt3724 applications. the total maximum power dissipation of the mosfet is the sum of these two loss terms: p fet(total) = p cond + p tran to achieve high supply ef? ciency, keep the p fet(total) to less than 3% of the total output power. also, complete a thermal analysis to ensure that the mosfet junction temperature is not exceeded. t j = t a + p fet(total) ? ja where ja is the package thermal resistance and t a is the ambient temperature. keep the calculated t j below the maxi- mum speci? ed junction temperature, typically 150c. note that when v in is high, the transition losses may dominate. a mosfet with higher r ds(on) and lower c rss may provide higher ef? ciency. mosfets with higher volt- age v dss speci? cation usually have higher r ds(on) and lower c rss . choose the mosfet v dss speci? cation to exceed the maximum voltage across the drain to the source of the mosfet, which is v in(max) plus any additional ringing on the switch node. ringing on the switch node can be greatly reduced with good pcb layout and, if necessary, an rc snubber. the internal v cc regulator operating range limits the maxi- mum total mosfet gate charge, q g , to 90nc. the q g vs v gs speci? cation is typically provided in the mosfet data sheet. use q g at v gs of 8v. if v cc is back driven from an external supply, the mosfet drive current is not sourced from the internal regulator of the lt3724 and the q g of the mosfet is not limited by the ic. however, note that the mosfet drive current is supplied by the internal regulator when the external supply back driving v cc is not available such as during startup or short-circuit. the manufacturers maximum continuous drain current speci? cation should exceed the peak switch current, i out(max) + i l /2. during the supply startup, the gate drive levels are set by the v cc voltage regulator, which is approximately 8v. once the supply is up and running, the v cc can be back driven by an auxiliary supply such as v out . it is important not to exceed the manufacturers maximum v gs speci? cation. a standard level threshold mosfet typically has a v gs maximum of 20v. step-down converter: recti? er selection the recti? er diode (d1 on the functional diagram) in a buck converter generates a current path for the inductor current when the main power switch is turned off. the recti? er is selected based upon the forward voltage, re- verse voltage and maximum current. a schottky diode is recommended. its low forward voltage yields the lowest power loss and highest ef? ciency. the maximum reverse voltage that the diode will see is v in(max) . in continuous mode operation, the average diode cur- rent is calculated at maximum output load current and maximum v in : i diode(avg) = i out(max) v in(max) v out v in(max ) to improve ef? ciency and to provide adequate margin for short-circuit operation, a diode rated at 1.5 to 2 times the maximum average diode current, i diode(avg) , is recom- mended.
lt3724 14 3724fc applications information step-down converter: input capacitor selection a local input bypass capacitor is required for buck convert- ers because the input current is pulsed with fast rise and fall times. the input capacitor selection criteria are based on the bulk capacitance and rms current capability. the bulk capacitance will determine the supply input ripple voltage. the rms current capability is used to keep from overheating the capacitor. the bulk capacitance is calculated based on maximum input ripple, v in : c in(bulk) = i out(max) ?v out v in ?f sw ?v in(min ) v in is typically chosen at a level acceptable to the user. 100mv-200mv is a good starting point. aluminum elec- trolytic capacitors are a good choice for high voltage, bulk capacitance due to their high capacitance per unit area. the capacitor?s rms current is: i cin(rms) = i out v out (v in ?v out ) (v in ) 2 if applicable, calculate it at the worst case condition, v in = 2v out . the rms current rating of the capacitor is speci? ed by the manufacturer and should exceed the calculated i cin(rms) . due to their low esr (equivalent series resistance), ceramic capacitors are a good choice for high voltage, high rms current handling. note that the ripple current ratings from aluminum electrolytic capacitor manufacturers are based on 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. the combination of aluminum electrolytic capacitors and ceramic capacitors is an economical approach to meet- ing the input capacitor requirements. the capacitor volt- age rating must be rated greater than v in(max) . multiple capacitors may also be paralleled to meet size or height requirements in the design. locate the capacitor very close to the mosfet switch and use short, wide pcb traces to minimize parasitic inductance. step-down converter: output capacitor selection the output capacitance, c out , selection is based on the designs output voltage ripple, v out , and transient load requirements. v out is a function of i l and the c out esr. it is calculated by: v out = i l ?esr + 1 (8 ? f sw ?c out ) the maximum esr required to meet a v out design requirement can be calculated by: esr(max) = ( v out )(l)(f sw ) v out ?1? v out v in(max ) worst-case v out occurs at highest input voltage. use paralleled multiple capacitors to meet the esr require- ments. increasing the inductance is an option to lower the esr requirements. for extremely low v out , an additional lc ? lter stage can be added to the output of the supply. application note 44 has some good tips on sizing an ad- ditional output ? lter. output voltage programming a resistive divider sets the dc output voltage according to the following formula: r2 = r1 v out 1.231 v ?1 the external resistor divider is connected to the output of the converter as shown in figure 2. tolerance of the feedback resistors will add additional error to the output voltage. example: v out = 12v; r1 = 10k r2 = 10k 12v 1.231 v 1 = 87.48k use 86.6k 1%
lt3724 15 3724fc applications information the v fb pin input bias current is typically 25na, so use of extremely high value feedback resistors could cause a converter output that is slightly higher than expected. bias current error at the output can be estimated as: v out(bias) = 25na ? r2 supply uvlo and shutdown the shdn pin has a precision voltage threshold with hysteresis which can be used as an undervoltage lockout threshold (uvlo) for the power supply. undervoltage lockout keeps the lt3724 in shutdown until the supply input voltage is above a certain voltage programmed by the user. the hysteresis voltage prevents noise from falsely tripping uvlo. resistors are chosen by ? rst selecting rb. then ra = rb ? v supply(on) 1.35 v ?1 v supply(on) is the input voltage at which the undervoltage lockout is disabled and the supply turns on. example: select rb = 49.9k, v supply(on) = 14.5v (based on a 15v minimum input voltage) ra = 49.9k ? 14.5v 1.35 v ?1 = 486.1k (499k resistor is selected) if low supply current in standby mode is required, select a higher value of rb. the supply turn off voltage is 9% below turn on. in the example the v supply(off) would be 13.2v. if additional hysteresis is desired for the enable function, an external positive feedback resistor can be used from the lt3724 regulator output. the shutdown function can be disabled by connecting the shdn pin to the v in through a large value pull-up resistor. this pin contains a low impedance clamp at 6v, so the shdn pin will sink current from the pull-up resistor(r pu ): i shd n = v in ?6v r p u because this arrangement will clamp the shdn pin to the 6v, it will violate the 5v absolute maximum voltage rating of the pin. this is permitted, however, as long as the absolute maximum input current rating of 1ma is not exceeded. input shdn pin currents of <100a are recommended: a 1m or greater pull-up resistor is typically used for this con? guration. soft-start the soft-start function forces the programmed slew rate while the converter output rises to 95% of regulation, which corresponds to 1.185v on the v fb pin. once 95% regulation is achieved, the soft-start circuit is disabled. the soft-start circuit will re-enable when the v fb pin drops below 70% of regulation, which corresponds to 300mv of control hysteresis on the v fb pin. this allows for a controlled recovery from a brown-out condition. figure 2. output voltage feedback divider figure 3. undervoltage lockout circuit l1 v fb pin r2 r1 v out c out 3724 f02 shdn pin ra rb v supply 3724 f03 figure 4.soft-start circuit r ss lt3724 v out c ss1 c ss 3724 f04 a
lt3724 16 3724fc applications information the desired soft-start rise time (t ss ) is programmed via a programming capacitor c ss1 , using a value that cor- responds to 2a average current during the soft-start interval. this capacitor value follows the relation: c ss1 = 2?10 ?6 ?t ss v ou t r ss is typically set to 200k for most applications. considerations for low-voltage output applications the lt3724 c ss pin biases to 220mv during the soft-start cycle, and this voltage is increased at figure 4 node a by the 2a signal current through r ss , so the output has to reach this value before the soft-start function is engaged. the value of this output soft-start startup voltage offset (v out(ss) ) follows the relation: v out(ss) = 220mv + r ss ? 2 ? 10 C6 which is typically 0.64v for r ss = 200k. in some low voltage output applications, it may be desir- able to reduce the value of this soft-start startup voltage offset. this is possible by reducing the value of r ss . with reduced values of r ss , the signal component caused by voltage ripple on the output must be minimized for proper soft-start operation. peak-to-peak output voltage ripple (v out ) will be imposed on node a through the capacitor c ss1 . the value of r ss can be set using the following equation: r ss = v out 1.3 ? 10 ? 6 it is important to use low esr output capacitors for lt3724 voltage converter designs to minimize this ripple voltage component. a design with an excessive ripple component can be evidenced by observing the v c pin during the start cycle. the soft-start cycle should be evaluated to verify that the reduced r ss value allows operation without excessive modulation of the v c pin before ? nalizing the design. if v c pin has an excessive ripple component during the soft-start cycle, converter output ripple should be reduced. this is typically accomplished by increasing output capaci- tance and/or reducing output capacitor esr. external current limit foldback circuit an additional startup voltage offset can occur during the period before the lt3724 soft-start circuit becomes ac- tive. before the soft-start circuit throttles back the v c pin in response to the rising output voltage, current as high as the peak programmed current limit (i max ) can ? ow in the switched inductor. switching will stop once the soft- start circuit takes hold and reduces the voltage on the v c pin, but the output voltage will continue to increase as the stored energy in the inductor is transferred to the output capacitor. with i max in the inductor, the resulting leading-edge rise on v out due to energy stored in the inductor follows the relation: v out = i max ? l c ou t 1/ 2 figure 6. desirable soft-start characteristic figure 5. soft-start characteristic showing excessive ripple component time, 250 s/div v(v c ) v out(ss) v out 3724 f05 time, 250 s/div 3724f06 v(v c ) v out(ss) v out
lt3724 17 3724fc applications information inductor current typically doesnt reach i max in the few cycles that occur before soft-start becomes active, but can with high input voltages or small inductors, so the above relation is useful as a worst-case scenario. this energy transfer increase in output voltage is typically small, but for some low voltage applications with relatively small output capacitors, it can become signi? cant. the volt- age rise can be reduced by increasing output capacitance, which puts additional limitations on c out for these low voltage supplies. another approach is to add an external current limit foldback circuit which reduces the value of i max during start-up. an external current limit foldback circuit can be easily incorporated into an lt3724 dc/dc converter application by placing a 1n4148 diode and a 47k resistor from the converter output (v out ) to the lt3724s v c pin. this limits the peak current to 0.25 ? i max when v out = 0v. a cur- rent limit foldback circuit also has the added advantage of providing reduced output current in the dc/dc converter during short-circuit fault conditions, so a foldback circuit may be useful even if the soft-start function is disabled. if the soft-start circuit is disabled by shorting the c ss pin to ground, the external current limit foldback circuit must be modi? ed by adding an additional diode and resistor. the 2-diode, 2-resistor network shown also provides 0.25 ? i max when v out = 0v. ef? ciency considerations the ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. express percent ef? ciency as: % ef? ciency = 100% - (l1 + l2 + l3 + ...) where l1, l2, etc. are individual loss terms as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main contributors usually account for most of the losses in lt3724 circuits: 1. lt3724 v in and v cc current loss 2. i 2 r conduction losses 3. mosfet transition loss 4. schottky diode conduction loss 1. the v in and v cc currents are the sum of the quiescent currents of the lt3724 and the mosfet drive currents. the quiescent currents are in the lt3724 electrical char- acteristics table. the mosfet drive current is a result of charging the gate capacitance of the power mosfet each cycle with a packet of charge, q g . q g is found in the mosfet data sheet. the average charging current is calculated as q g ? f sw . the power loss term due to these currents can be reduced by backdriving v cc with a lower voltage than v in such as v out . figure 7. current limit foldback circuit for applications that use soft-start 1n4148 47k v out v c 3724 f03 figure 8. current limit foldback circuit for applications that have soft-start disabled (c ss pin shorted to sgnd) 1n4148 27k 39k v out v c 3724 f07 1n4148
lt3724 18 3724fc applications information 2. i 2 r losses are calculated from the dc resistances of the mosfet, the inductor, the sense resistor, and the input and output capacitors. in continuous conduction mode the aver- age output current ? ows through the inductor and r sense but is chopped between the mosfet and the schottky diode. the resistances of the mosfet (r ds(on) ) and the r sense multiplied by the duty cycle can be summed with the resistances of the inductor and r sense to obtain the total series resistance of the circuit. the total conduction power loss is proportional to this resistance and usually accounts for between 2% to 5% loss in ef? ciency. 3. transition losses of the mosfet can be substantial with input voltages greater than 20v. see mosfet selection section. 4. the schottky diode can be a major contributor of power loss especially at high input to output voltage ratios (low duty cycles) where the diode conducts for the majority of the switch period. lower v f reduces the losses. note that oversizing the diode does not always help because as the diode heats up the v f is reduced and the diode loss term is decreased. i 2 r losses and the schottky diode loss dominate at high load currents. other losses including c in and c out esr dissipative losses and inductor core losses generally ac- count for less than 2% total additional loss in ef? ciency. pcb layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation. these items are illustrated graphically in the layout diagram of figure 9. 1. keep the signal and power grounds separate. the signal ground consists of the lt3724 sgnd pin, the exposed pad on the backside of the lt3724 ic and the (C) terminal of v out . the signal ground is the quiet ground and does not contain any high, fast currents. the power ground consists of the schottky diode anode, the (C) terminal of the input capacitor, and the ground return of the v cc capacitor. this ground has very fast high currents and is considered the noisy ground. the two grounds are connected to each other only at the (C) terminal of v out . 2. use short wide traces in the loop formed by the mosfet, the schottky diode and the input capacitor to minimize high frequency noise and voltage stress from parasitic inductance. surface mount components are preferred. 3. connect the v fb pin directly to the feedback resistors independent of any other nodes, such as the sense C pin. connect the feedback resistors between the (+) and (C) terminals of c out . locate the feedback resistors in close proximity to the lt3724 to keep the high impedance node, v fb , as short as possible. 4. route the sense C and sense + traces together and keep as short as possible. 5. locate the v cc and boost capacitors in close proximity to the ic. these capacitors carry the mosfet drivers high peak currents. place the small signal components away from high frequency switching nodes (boost, sw, and tg). in the layout shown in figure 9, place all the small signal components on one side of the ic and all the power components on the other. this helps to keep the signal and power grounds separate. 6. a small decoupling capacitor (100pf) is sometimes useful for ? ltering high frequency noise on the feedback and sense nodes. if used, locate as close to the ic as possible. 7. the lt3724 packaging will ef? ciently remove heat from the ic through the exposed pad on the backside of the part. the exposed pad is soldered to a copper footprint on the pcb. make this footprint as large as possible to improve the thermal resistance of the ic case to ambient air. this helps to keep the lt3724 at a lower temperature. 8. make the trace connecting the gate of mosfet m1 to the tg pin of the lt3724 short and wide.
lt3724 19 3724fc applications information minimum on-time considerations (step-down converters) minimum on-time (t tg(on) ) is the least amount of time that the lt3724 is capable of turning the mosfet on and then off again. it is determined by internal timing delays and the gate charge of the mosfet. applications with high input to output differential voltages operate at low duty cycles and may approach this minimum on-time, typically 300ns. the lt3724 switching frequency is internally set to 200khz, therefore, the minimum duty cycle of the mosfet switch is 6%. when the duty cycle needs to be less than 6% the output will stay regulated, but cycle skipping may occur. cycle skipping results in an increase in inductor ripple current. if it is important that cycle skipping does not occur, follow this guideline which takes into account worst case f sw and t tg(on) : v in(max) 9 ? v out this is only an issue for supplies with v out < 7v. figure 9. lt3724 layout diagram (see pcb layout checklist). 4 c boost r sense r a r c r2 r1 r b r css v in C v in + v in shdn c ss burst_en v fb v c sgnd boost tg sw v cc pgnd sense + sense C + C l1 m1 d3 3724 f06 lt3724 1 3 5 6 7 8 16 15 14 12 11 10 9 d2 d1 c vcc c in c out v out c c2 c c1 c ss 17
lt3724 20 3724fc typical applications 12v to 24v/50w boost (step-up) converter ef? ciency and power loss vs load current 4 r3 4.7m r6 40.2k r2 187k r1 10k v in shdn c ss burst_en v fb v c sgnd boost tg sw v cc pgnd sense + sense C m1 d2 sbm540 3724 ta02 lt3724 1 3 5 6 7 8 16 15 14 12 11 10 9 c3 4700pf c2 120pf c4 1 f 25v c1 1500pf 0.1 f 25v c out1 330 f 35v c out2 2.2 f x3 50v c in = sanyo, 25svp33m l1 = vishay, ihlp-5050fd-011 m1 = siliconix, si7370dp c out1 = sanyo, 35cv330axa c out2 = tdk, c4532x7r1h225k d2 = diodesinc., sbm540 r sense = irc lrf2512-01-r0i5-f c in 33 f 2 25v v in 8v to16v r sense 0.015 l1 10 h v out 24v at 50w r css 200k d1 bav99 load current (a) 0.1 efficiency (%) power loss (w) 100 98 96 94 92 90 88 3.0 2.5 2.0 1.5 1.0 0 0.5 110 3724 f08 v in = 8v v in = 12v v in = 16v loss v in = 12v
lt3724 21 3724fc typical applications high voltage led driver with dimmer control 4.5v to 20v input to 12v at 25w output sepic converter with 60v input transient capability ef? ciency and power loss vs load current 4 v in shdn c ss burst_en v fb v c sgnd boost tg sw v cc pgnd sense + sense C m1 zxmn10a07f m2 2n7002 optional dimmer control 1khz 3724 ta03 lt3724 1 3 5 6 7 8 16 15 14 12 11 10 9 c vcc 1 f 16v c1 100pf r1 4.7m r sense 0.5 l1 300 h led v in 8v to 60v c1 = optional to reduce led ripple current c in = tdk, c4532x7r2a225k d1 = diodesinc., b170 m1 = zetex, zxmn10a07f r sense = vishay, wsl2010r0150fea l1 = coiltronics, ctx300-4 adjust i led : i led = 0.15v r sense c1 (optional) d1 b170 4 rb 49.9k ra 100k r5 40.2k r sense 0.010 r2 130k r1 14.7k shdn c ss r3 200k burst_en v fb v c sgnd tg sw v cc pgnd sense + sense C 1 3 5 6 7 8 16 15 14 12 11 10 9 c3 680pf c2 120pf r4 47k c7 0.1 f c1 390pf c in2 25v 1 f c in1 22 f 2x 25v v in 4.5v to 20v to 60v transient d1a gsd2004 d3 d1n4148 l1 20 h l1 20 h d1b gsd2004 d2 v out 12v at 25w c out2 22 f m1 3724 ta07a v in boost lt3724 c4 1 f 25v c out1 330 f 25v 16v c6 56pf r7 10 r6 10 c5 22 f 3x 25v ? ? c5, c in1 , c out2 = tdkc453x7r1e226m c out1 = sanyo, os-con 16svp330m d2 = on semi, mbrd660 l1 = coilcraft versapac vp5-d83 m1 = vishay, si7852dp load current (a) 0.1 efficiency (%) power loss (w) 92 91 90 89 88 87 86 85 3.5 3.0 2.5 2.0 1.5 1.0 0 0.5 110 3724 ta07b v in = 20v v in = 10v v in = 15v loss v in = 15v
lt3724 22 3724fc typical applications 12v step-down with v cc back driven from v out and ceramic capacitor in output filter 4 r3 49.9k r7 20 r2 499k r6 15k r4 130k r5 14.7k v in shdn c ss r css 200k burst_en v fb v c sgnd boost tg sw v cc pgnd sense + sense C 3724 ta04 lt3724 1 3 5 6 7 8 16 15 14 12 11 10 9 c3 680pf c2 120pf c4 1 f 16v c6 0.1 f 16v c1 3300pf c in 100 f 100v 2.2 f x2 100v v in 15v to 60v d2b bav99 l1 47 h d1 d2a bav99 r sense 0.020 v out 12v at 50w c out 33 f x3 16v c in : tdk, c4532x7r2a225mt c out : tdk, c4532x7r1c336mt d1: diodesinc., pds5100h l1: coev du1971-470m m1: vishay si7852dp m1 si7852dp +
lt3724 23 3724fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. fe16 (bc) tssop 0204 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 134 5 6 7 8 10 9 4.90 ? 5.10* (.193 ? .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 2.94 (.116) 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc package description fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation bc
lt3724 24 3724fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 1008 rev c ? printed in usa related parts typical application inverting C12v 1.5a converter c c2 680pf c c1 120pf r6, 40.2k c ss 1000pf r css 200k r2 10.2k r1 88.7k 0.1 f 0.1 f 16v 1 f 16v r3 2m v in 18v to 36v v in shdn c ss v fb v c gnd boost tg sw v cc pgnd sense + sense C + + v out C12v 1.5a c out1 330 f 16v c in1 220 f 50v l1 47 h m1 d2 d1b d1a r sense 0.040 d1 = bav99 d2 = on semi, mbrd350 l1 = coev, du1311-470m m1 = vishay, si7370dp c in1 = sanyo, 50cv220kx c out1 = sanyo, 16svp330m 3724 ta05 lt3724 4 1 3 6 7 8 16 15 14 11 10 9 12 part number description comments lt1339 high power synchronous dc/dc controller v in up to 60v, drivers 10000pf gate capacitance, i out = <20a ltc1624 switching controller buck, boost, sepic, 3.5v v in 36v; 8-lead so package ltc1702a dual 2-phase synchronous dc/dc controller 550khz operation, no r sense , 3v =

▲Up To Search▲

Price & Availability of 3724MPFE

	To Download 3724MPFE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .